Mesh-Structured On-Chip Power/Ground: Design for Minimum Inductance and Characterization for Fast R, L Extraction
نویسندگان
چکیده
Abstract: For high-speed circuits, on-chip inductance can no longer be ignored. This paper deals with inductance in the presence of multi-layered meshes used for on-chip power supplies. We have shown ways of designing power/ground (p/g) mesh that reduce inductance. Accurate 3-dimensional inductance extraction problem is intractable for large chips. We have demonstrated the feasibility of using flexible-accuracy empirical formulae for fast determination of inductance. We have reported results obtained from a real chip.
منابع مشابه
High Frequency Characterization and Modeling of VLSI On-Chip Interconnects
| Modeling of on-chip inductance for chips with realistic power/ground wires and grids is presented. Analytical formulae as well as eld solvers are used to analyze inductance of on-chip structures including power/ground grids, ground plane and substrate e ects. Insights and design guidelines to reduce wire inductance are demonstrated. An accurate capacitance modeling approach is also presented.
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